Verilog · Beginners · Two weeks with verilog-newbie: what feels right and what drives me up the wall

There is actually a simpler fix that needs no architecture change: move this check up to the gateway and the problem disappears. The cost is one extra lookup at the gateway.

A question: what changes in a container with a 512Mi memory limit? That is how we run it in production.

Worth learning from this debugging approach. We went straight at the logs and took a much longer route.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

Can you give a minimal reproduction? I ran it locally for ten minutes and could not reproduce on macOS with the latest version.

This matches what we see in production. We only hit it past 3k QPS; the earlier load tests showed nothing — the test traffic was too clean, with no long-tail requests.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

This is not a verilog-newbie problem, it is a usage problem. The docs say this API is not thread-safe and you must lock around it yourself.

There is actually a simpler fix that needs no architecture change: move this check up to the gateway and the problem disappears. The cost is one extra lookup at the gateway.

Has anyone run a controlled experiment? I did, reducing it to a single variable, and the difference was 4% — within noise. So I suspect the main cause is something else.

This matches what we see in production. We only hit it past 3k QPS; the earlier load tests showed nothing — the test traffic was too clean, with no long-tail requests.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

Has anyone run a controlled experiment? I did, reducing it to a single variable, and the difference was 4% — within noise. So I suspect the main cause is something else.

There is actually a simpler fix that needs no architecture change: move this check up to the gateway and the problem disappears. The cost is one extra lookup at the gateway.

One counter-example: below verilog-newbie 7.4 the semantics of that code are different, so do not copy it verbatim. We got burned in staging and rolled back once.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

We have run this in production for two years without hitting it. That said, we never reached this scale, so our experience is not really evidence here.

Sharing our numbers, 8 cores 16GB, same scenario:

| Concurrency | P50 | P99 |
|---|---|---|
| 200 | 12ms | 88ms |
| 500 | 31ms | 340ms |

P99 clearly collapses at 500 concurrency, which lines up with your knee point.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.