ESP32 · Code review · I upgraded our production esp32-review and hit these 11 landmines

Worth learning from this debugging approach. We went straight at the logs and took a much longer route.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

This matches what we see in production. We only hit it past 3k QPS; the earlier load tests showed nothing — the test traffic was too clean, with no long-tail requests.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

Has anyone run a controlled experiment? I did, reducing it to a single variable, and the difference was 4% — within noise. So I suspect the main cause is something else.

There is actually a simpler fix that needs no architecture change: move this check up to the gateway and the problem disappears. The cost is one extra lookup at the gateway.

Saved. I am reworking this area this week — this saves a lot of wrong turns.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

Sharing our numbers, 8 cores 16GB, same scenario:

| Concurrency | P50 | P99 |
|---|---|---|
| 200 | 12ms | 88ms |
| 500 | 31ms | 340ms |

P99 clearly collapses at 500 concurrency, which lines up with your knee point.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

One counter-example: below esp32-review 7.4 the semantics of that code are different, so do not copy it verbatim. We got burned in staging and rolled back once.

One counter-example: below esp32-review 7.4 the semantics of that code are different, so do not copy it verbatim. We got burned in staging and rolled back once.

One counter-example: below esp32-review 7.4 the semantics of that code are different, so do not copy it verbatim. We got burned in staging and rolled back once.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

Agreeing with the above. One addition: with this option enabled the GC count in your metrics doubles, so adjust the alert threshold at the same time or it will keep firing.

Worth learning from this debugging approach. We went straight at the logs and took a much longer route.

This is not a esp32-review problem, it is a usage problem. The docs say this API is not thread-safe and you must lock around it yourself.

Can you give a minimal reproduction? I ran it locally for ten minutes and could not reproduce on macOS with the latest version.

We have run this in production for two years without hitting it. That said, we never reached this scale, so our experience is not really evidence here.

Worth learning from this debugging approach. We went straight at the logs and took a much longer route.

Saved. I am reworking this area this week — this saves a lot of wrong turns.

Sharing our numbers, 8 cores 16GB, same scenario:

| Concurrency | P50 | P99 |
|---|---|---|
| 200 | 12ms | 88ms |
| 500 | 31ms | 340ms |

P99 clearly collapses at 500 concurrency, which lines up with your knee point.

I just read the esp32-review source — the author actually explains the reasoning in a comment, roughly "so that it degrades into predictable behaviour in extreme cases".

I just read the esp32-review source — the author actually explains the reasoning in a comment, roughly "so that it degrades into predictable behaviour in extreme cases".

Agreeing with the above. One addition: with this option enabled the GC count in your metrics doubles, so adjust the alert threshold at the same time or it will keep firing.

Can you give a minimal reproduction? I ran it locally for ten minutes and could not reproduce on macOS with the latest version.

This matches what we see in production. We only hit it past 3k QPS; the earlier load tests showed nothing — the test traffic was too clean, with no long-tail requests.

We have run this in production for two years without hitting it. That said, we never reached this scale, so our experience is not really evidence here.

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

Agreeing with the above. One addition: with this option enabled the GC count in your metrics doubles, so adjust the alert threshold at the same time or it will keep firing.

A question: what changes in a container with a 512Mi memory limit? That is how we run it in production.

Agreeing with the above. One addition: with this option enabled the GC count in your metrics doubles, so adjust the alert threshold at the same time or it will keep firing.

A question: what changes in a container with a 512Mi memory limit? That is how we run it in production.

Has anyone run a controlled experiment? I did, reducing it to a single variable, and the difference was 4% — within noise. So I suspect the main cause is something else.

A question: what changes in a container with a 512Mi memory limit? That is how we run it in production.

There is actually a simpler fix that needs no architecture change: move this check up to the gateway and the problem disappears. The cost is one extra lookup at the gateway.

I see point 3 differently. The trade-off depends on your read/write ratio: read-heavy with little writing means caching actually widens the inconsistency window.

I just read the esp32-review source — the author actually explains the reasoning in a comment, roughly "so that it degrades into predictable behaviour in extreme cases".

Thanks for sharing real numbers — far more useful than the articles that only cover concepts.

Saved. I am reworking this area this week — this saves a lot of wrong turns.

I just read the esp32-review source — the author actually explains the reasoning in a comment, roughly "so that it degrades into predictable behaviour in extreme cases".